MPC8540 datasheet(374/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-20

Freescale Semiconductor

DDR Memory Controller

9.4.1.12 Memory Data Path Read Capture Low (CAPTURE_DATA_LO)

The memory data path read capture low register, shown in Figure 9-13, stores the low word of the

read data path during error capture.

Figure 9-13. Memory Data Path Read Capture Low Register (CAPTURE_DATA_LO)

Table 9-17 describes the CAPTURE_DATA_LO fields.

9.4.1.13 Memory Data Path Read Capture ECC (CAPTURE_ECC)

The memory data path read capture ECC register, shown in Figure 9-14, stores the ECC syndrome

bits that were on the data bus when an error was detected.

Figure 9-14. Memory Data Path Read Capture ECC Register (CAPTURE_ECC)

Table 9-18 describes the CAPTURE_ECC fields.

ECLD

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2E24

Table 9-17. CAPTURE_DATA_LO Field Descriptions

Bits

Name

Description

0–31

ECLD

Error capture low data path. Captures the low word of the data path when errors are detected.

23 24

R 000000000000000000000000

ECE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2E28

Table 9-18. CAPTURE_ECC Field Descriptions

Bits

Name

Description

0–23

—

Reserved

24–31

ECE

Error capture ECC. Captures the ECC bits on the data path whenever errors are detected.

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