MPC8540 datasheet(378/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-24

Freescale Semiconductor

DDR Memory Controller

9.4.1.18 Memory Error Address Capture (CAPTURE_ADDRESS)

The memory error address capture register, shown in Figure 9-19, holds the 32 lsbs of a transaction

when a DDR ECC error is detected.

Figure 9-19. Memory Error Address Capture Register (CAPTURE_ADDRESS)

Table 9-23 describes the CAPTURE_ADDRESS fields.

11–15

TSRC

Transaction source for the error

00000 PCI

00001–00011 Reserved

00100 Local bus

00101–00111 Reserved

01000 Configuration space

01001 Reserved

01010 Boot sequencer

01011 Reserved

01100 RapidIO

01101–01111 Reserved

10000 Processor (instruction)

10001 Processor (data)

10010–10011 Reserved

10100 Reserved

10101 DMA

10110 Reserved

10111 SAP

11000 TSEC1

11001 TSEC2

11010 FEC

11011 Reserved

11100 RapidIO message units

11101 RapidIO doorbell units

11110 RapidIO port—write units

11111 Reserved

16–17

—

Reserved

18–19

TTYP

Transaction type for the error

00 Reserved

01 Write

10 Read

11 Read-modify-write

20–30

—

Reserved

VLD

Valid. Set as soon as valid information is captured in the error capture registers.

CADDR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2E50

Table 9-23. CAPTURE_ADDRESS Field Descriptions

Bits

Name

Description

0–31

CADDR Captured address. Captures the 32 lsbs of the transaction address when an error is detected.

Table 9-22. CAPTURE_ATTRIBUTES Field Descriptions (continued)

Bits

Name

Description

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