MPC8540 datasheet(379/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-25

9.4.1.19 Single-Bit ECC Memory Error Management (ERR_SBE)

The single-bit ECC memory error management register, shown in Figure 9-20, stores the threshold

value for reporting single-bit errors and the number of single-bit errors counted since the last error

report. When the counter field reaches the threshold, it wraps back to the reset value (0). If

necessary, software must clear the counter after it has managed the error.

Figure 9-20. Single-Bit ECC Memory Error Management Register (ERR_SBE)

Table 9-24 describes the ERR_SBE fields.

9.5

Functional Description

The DDR SDRAM controller controls processor and I/O interactions with system memory. It

provides support for JEDEC-compliant DDR SDRAMs (first generation dual data rate). The

memory system allows a wide range of memory devices to be mapped to any arbitrary chip select.

However, registered DIMMs cannot be mixed with unbuffered DIMMs.

Figure 9-21 is a high-level block diagram of the DDR memory controller. Requests are received

from the internal mastering device and the address is decoded to generate the physical bank,

logical bank, row, and column addresses. The transaction is then loaded into the input staging

queue with the decoded information. The lower two entries of the input queue are compared with

values in the row open table to determine if the address maps to an open page. If the address from

either entry does not map to an open page, an activate command is issued for the entry that did not

hit an open page, with the lowest entry having priority over the next lowest. Commands are always

issued from the lowest input queue entry.

15 1623 2431

R 0

0000000

SBET

00000000

SBEC

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x0_2E58

Table 9-24. ERR_SBE Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–15

SBET Single-bit error threshold. Establishes the number of single-bit errors that must be detected before an

error condition is reported.

16–23

—

Reserved

24–31

SBEC Single-bit error counter. Indicates the number of single-bit errors detected and corrected since the last

error report. If single-bit error reporting is enabled, an error is reported and an interrupt is generated

when this value equals SBET. SBEC is automatically cleared when the threshold value is reached.

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