 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MPC8540 Datasheet(PDF) 383 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8540 Datasheet(HTML) 383 Page - Freescale Semiconductor, Inc |
|
|
383 / 1302 page  Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 9-29 Figure 9-25. Example 256-Mbyte DDR SDRAM Configuration with ECC CAS CS RAS CKE CLK DM A[0-11] 2 Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A(11-0) 2 Mx8 SDRAM DQ(7-0) BA(1-0) CAS CS RAS CKE CLK DM A(11-0) 2Mx8 SDRAM DQ(7-0) BA(1-0) CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS WE CKE CK DM A[11:0] 8M ×8 SDRAM DQ[7:0] BA[1:0] 0 MDQ[0:7] MDQ[8:15] MDQ[16:23] MDQ[24:31] MDQ[32:39] MDQ[40:47] MDQ[48:55] MDQ[56:63] 1 2 3 4 5 6 7 0 MDQ[0:7] 1 2 3 4 5 6 7 CAS CS RAS CKE CK DM A[11:0] 8M ×8 SDRAM DQ[7:0] BA[1:0] 8 ECC[0:7] MRAS MCAS MWE MCKE MCK[0:5] MCS[0:3] MBA[0:1] MA[0:14] MDQ[0:63] MECC[0:7] MDM[0:8] MCS0 MCS1 Bank 1 8M ×72 (64 Mbytes) To all SDRAM Devices in Common Memory Data Bus and Strobes Bank 0 8M ×72 (64 Mbytes) CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A[0-11] 2 Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CLK DM A(11-0) 2Mx8 SDRAM DQ(7-0) BA(1-0) CAS CS RAS CKE CLK DM A(11-0) 2 Mx8 SDRAM DQ(7-0) BA(1-0) CAS CS RAS CKE CLK DM A[0-11] 2Mx8 SDRAM DQ[0-7] BA[0-1] CAS CS RAS CKE CK DM A[11:0] 8M ×8 SDRAM DQ[7:0] BA[1:0] MDQ[8:15] MDQ[16:23] MDQ[24:31] MDQ[32:39] MDQ[40:47] MDQ[48:55] MDQ[56:31] Banks 2 –3 MDQS[0] MDQS MDQS[7] MDQS[8] MDQS MDQS[0] MDQS MDQS[7] MDQS[0:8] 4. MCK[0:5] may be apportioned among all memory devices. Complementary bus is not shown. 3. Buffering may be needed if large memory arrays are used. 2. Each of the MCS[0:3] signals correspond with a separate physical bank of memory. 1. All signals are connected in common (in parallel) except for MCS[0:3],MCK[0:5], MDM[0:8], and the data bus signals. DDR Controller CAS CS RAS CKE CK DM A[11:0] 8M ×8 SDRAM DQ[7:0] BA[1:0] 8 ECC[0:7] MDQS[8] MDQS MCK[0:5] WE WE WE |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
