MPC8540 datasheet(387/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-33

The following DDR SDRAM interface commands (summarized in Table 9-28) are provided by the

DDR controller. All actions for these commands are described from the perspective of the

SDRAM device.

•

Row activate—Latches row address and initiates memory read of that row. Row data is

latched in SDRAM sense amplifiers and must be restored by a precharge command before

another row activate occurs.

•

Precharge—Restores data from the sense amplifiers to the appropriate row. Also initializes

the sense amplifiers in preparation for reading another row in the memory array,

(performing another activate command). Precharge must occur after read or write, if the

row address changes on the next open page mode access.

•

Read—Latches column address and transfers data from the selected sense amplifier to the

output buffer as determined by the column address. During each succeeding clock edge,

additional data is driven without additional read commands. The amount of data transferred

is determined by the burst size which defaults to 4.

•

Write—Latches column address and transfers data from the data pins to the selected sense

amplifier as determined by the column address. During each succeeding clock edge,

additional data is transferred to the sense amplifiers from the data pins without additional

write commands. The amount of data transferred is determined by the burst size, which is

set to four by the DDR memory controller.

•

Refresh (similar to MCAS before MRAS)—Causes a row to be read in all logical banks

(JEDEC SDRAM) as determined by the refresh, row address counter. This refresh row

address counter is internal to the SDRAM. After being read, the row is automatically

rewritten in the memory array. All logical banks must be in a precharged state before

executing a refresh.

•

Mode register set (for configuration)—Allows setting of DDR SDRAM options. These

options are: MCAS latency, burst type, and burst length. MCAS latency may be chosen as

provided by the preferred SDRAM (some SDRAMs provide MCAS latency {1,2,3}, some

provide MCAS latency {1,2,3,4}, and so on). Burst type is always sequential. Although

some SDRAMs provide burst lengths of 1, 2, 4, 8, and page size, this memory controller

supports a burst length of 4. The mode register set command is performed by the DDR

memory controller during system initialization. Parameters such as mode register data,

MCAS latency, burst length, and burst type, are set by software in

DDR_SDRAM_MODE[SDMODE] and transferred to the SDRAM array by the DDR

memory controller after DDR_SDRAM_CFG[MEM_EN] is set.

•

Self refresh (for long periods of standby)—Used when the device is in standby for very long

periods of time. Automatically generates internal refresh cycles to keep the data in all

memory banks refreshed. Before execution of this command, all logical banks are in a

precharged state.

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