MPC8540 datasheet(388/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-34

Freescale Semiconductor

DDR Memory Controller

9.5.4

SDRAM Interface Timing

The DDR memory controller supports four-beat bursts to SDRAM. For single-beat reads, the DDR

memory controller performs a four-beat burst read, but ignores the last three beats. Single-beat

writes are performed by masking the last three beats of the four-beat burst using the data mask

MDM[0:8]. If ECC is disabled, writes smaller than double words are performed by appropriately

activating the data mask. If ECC is enabled, the controller performs a read-modify write.

NOTE

If a second read or write is pending, reads shorter than four beats are

not terminated early even if some data is irrelevant.

To accommodate available memory technologies across a wide spectrum of operating frequencies,

the DDR memory controller allows the setting of the intervals defined in Table 9-29 with

granularity of one memory clock cycle, except for CASLAT, which can be programmed with 1/2

clock granularity.

Table 9-28. SDRAM Command Table

Operation

CKE

Prev.

CKE

Current

MCS

MRAS

MCAS MWE

MBA

MA10

Activate

Logical bank

select

Row

Precharge select

logical bank

Logical bank

select

Precharge all

logical banks

Read

Logical bank

select

Column

Read with auto

precharge

Logical bank

select

Column

Write

Logical bank

select

Column

Write with auto

precharge

Logical bank

select

Column

Mode register set

Opcode

Opcode and mode

Auto refresh

Self refresh

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