MPC8540 datasheet(389/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-35

The value of the above parameters (in whole clock cycles) must be set by boot code at system

start-up (in the TIMING_CFG_1 and TIMING_CFG_2 registers as described in Section 9.4.1.3,

“DDR SDRAM Timing Configuration 1 (TIMING_CFG_1),” and Section 9.4.1.4, “DDR

SDRAM Timing Configuration 2 (TIMING_CFG_2)”) and be kept in the DDR memory controller

configuration register space.

The following figures show SDRAM timing for various types of accesses. System software is

responsible (at reset) for optimally configuring SDRAM timing parameters. The programmable

timing parameters apply to both read and write timing configuration. The configuration process

Table 9-29. DDR SDRAM Interface Timing Intervals

Timing

Intervals

Definition

ACTTOACT

The number of clock cycles from a bank-activate command until another bank-activate command

within a physical bank. This interval is listed in the AC specifications of the SDRAM.

ACTOPRE

The number of clock cycles from an activate command until a precharge command is allowed.

This interval is listed in the AC specifications of the SDRAM.

ACTORW

The number of clock cycles from an activate command until a read or write command is allowed.

This interval is listed in the AC specifications of the SDRAM.

BSTOPRE

The number of clock cycles to maintain a page open after an access. The page open duration

counter is reloaded with BSTOPRE each time the page is accessed (including page hits). When

the counter expires, the open page is closed with a SDRAM precharge bank command as soon as

possible.

CASLAT

READ latency. The number of clock cycles between the registration of a READ command by the

SDRAM and the availability of the first piece of output data. If a READ command is registered at

clock edge

n, and the latency is m clocks, the data is available nominally coincident with clock

edge

n + m.

PRETOACT

The number of clock cycles from a precharge command until an activate or a refresh command is

allowed. This interval is listed in the AC specifications of the SDRAM.

REFINT

Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. One

row is refreshed in each SDRAM bank during each refresh cycle. The value of REFINT depends

on the specific SDRAMs used and the frequency of the interface.

REFREC

The number of clock cycles from the refresh command until an activate command is allowed. This

can be calculated by referring to the AC specification of the SDRAM device. The AC specification

indicates a maximum refresh to activate interval in nanoseconds.

WR_DATA_

DELAY

Provides different options for the timing between a write command and the write data strobe. This

allows write data to be sent later than the nominal time to meet the SDRAM timing requirement

between the registration of a write command and the reception of a data strobe associated with

the write command. The specification dictates that the data strobe may not be received earlier

than 75% of a cycle, or later than 125% of a cycle, from the registration of a write command. This

parameter is not defined in the SDRAM specification. It is implementation-specific, defined for the

DDR memory controller in TIMING_CFG_2.

WRREC

The number of clock cycles from the last beat of a write until a precharge command is allowed.

This interval, write recovery time, is listed in the AC specifications of the SDRAM.

WRTORD

Last write pair to read command. Controls the number of clock cycles from the last write data pair

to the subsequent read command to the same bank.

MPC8540 Datasheet(PDF) 389 Page - Freescale Semiconductor, Inc

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