MPC8540 datasheet(392/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-38

Freescale Semiconductor

DDR Memory Controller

9.5.4.1

Clock Distribution

•

If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard,

should be used. These buffers were designed for DDR applications.

•

The DLL timing loop PCB route should mimic the MCK route as closely as possible,

although clock edges can be intentionally advanced or retarded by modifying this loop.

With all DDR clocks as nearly identical as possible, the single DLL timing loop can be

finely adjusted to advance or retard all of them.

•

A 72 bit

× 64 Mbytes DDR bank has 9-byte-wide DDR chips, resulting in 18 DDR chips

in a two-bank system. In this case, each MCK/MCK signal pair should drive exactly three

devices.

•

PCB traces for DDR clock signals should be short, all on the same layer, and of equal length

and loading as the DLL timing loop.

•

DDR SDRAM manufacturers provide detailed information on PCB layout and termination

issues.

Figure 9-29. DDR SDRAM Clock Distribution Example

9.5.5

DDR SDRAM Mode-Set Command Timing

The DDR memory controller transfers the extended mode and base mode register data

DDR_SDRAM_MODE[ESDMODE,SDMODE] to the SDRAM array by issuing two mode-set

commands separated by two SDRAM clock periods. Figure 9-30 shows the timing of the mode-set

command. The first transfer corresponds to the ESDMODE code; the second corresponds to

SDMODE. Following commands must wait two SDRAM cycles.

MCK[1], MCK[1]

MCK[2], MCK[2]

MCK[0], MCK[0]

DQ[0:7], DQS[0], DM[0]

DQ[8:15], DQS[1], DM[1]

DQ[16:23], DQS[2], DM[2]

DQ[24:31], DQS[3], DM[3]

DQ[32:39], DQS[4], DM[4]

DQ[40:47], DQS[5], DM[5]

DQ[48:55], DQS[6], DM[6]

DQ[56:63], DQS[7], DM[7]

ECC[0:7], DQS[8], DM[8]

DDR

CS[0]

A[13:0], BA[1:0], MRAS, MCAS, MWE, CKE

MCK[4], MCK[4]

MCK[5], MCK[5]

MCK[3], MCK[3]

CS[1]

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