MPC8540 datasheet(395/1302 Pages) FREESCALE

395 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-41

Figure 9-32. Write Timing Adjustments Example

9.5.8

DDR SDRAM Refresh

The DDR memory controller supports auto-refresh and self-refresh. Auto refresh is used during

normal operation and is controlled by the DDR_SDRAM_INTERVAL[REFINT] value;

self-refresh is used only when the DDR memory controller is set to enter a sleep power

management state or a soft-stop state. The REFINT value, which represents the number of

memory bus clock cycles between refresh cycles, must allow for possible outstanding transactions

to complete before a refresh request is sent to the memory after the REFINT value is reached. If a

memory transaction is in progress when the refresh interval is reached, the refresh cycle waits for

the transaction to complete. In the worst case, the refresh cycle must wait the number of bus clock

cycles required by the longest programmed access. To ensure that the latency caused by a memory

transaction does not violate the device refresh period, it is recommended that the programmed

value of REFINT be less than that required by the SDRAM.

ACTTORW

ROW

COL

SDRAM Clock

MCS

MCAS

MA[13:0]

MWE

MRAS

MDQ[0:63]

MDQS

MDM[0:7]

1/4 Delay

COL

MDQ[0:63]

MDQS

MDM[0:7]

1/2 Delay

8910

D0 D1 D2 D3 D0 D1 D2 D3

MPC8540 Datasheet(PDF) 395 Page - Freescale Semiconductor, Inc