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MPC8540 Datasheet(PDF) 397 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 397 Page - Freescale Semiconductor, Inc

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Functional Description
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
9-43
System software is responsible for optimal configuration of TIMING_CFG_1 [REFREC] at reset.
Configuration must be completed before DDR SDRAM accesses are attempted.
9.5.8.2
DDR SDRAM Refresh and Power-Saving Modes
In full-on mode, the DDR memory controller supplies the normal auto refresh to SDRAM. In sleep
mode, the DDR memory controller can be configured to take advantage of self-refreshing
SDRAMs or to provide no refresh support. Self-refresh support is enabled with the SREN memory
control parameter of the DDR_SDRAM_CFG register. Table 9-30 summarizes the refresh types
available in each power-saving mode.
Note that in the absence of refresh support, system software must preserve DDR SDRAM data
(such as by copying the data to disk) before entering the power-saving mode.
All open pages are precharged before self refresh mode is entered.
The dynamic power-saving mode uses the CKE DDR SDRAM pin to dynamically power down
when there is no system memory activity. The CKE pin is negated when both of the following
conditions are met:
•
No memory refreshes are scheduled.
•
No memory accesses are scheduled.
CKE is reasserted when a new access or refresh is scheduled or the dynamic power mode is
disabled. This mode is controlled with DDR_SDRAM_CFG[DYN_PWR].
Dynamic power management mode offers tight control of the memory system’s power
consumption by trading power for performance through the use of
DDR_SDRAM_INTERVAL[BSTOPRE]. Powering up the DDR SDRAM when a new memory
reference is scheduled causes a one-clock access latency penalty, as shown in Figure 9-34.
Figure 9-34. DDR SDRAM Power-Down Mode
Table 9-30. DDR SDRAM Power-Saving Modes Refresh Configuration
Power Saving
Mode
Refresh
Type
SREN
Sleep
Self
1
None
0
Mem Bus Clock
NOP
NOP
COMMAND
ACT
CKE



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