MPC8540 datasheet(400/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-46

Freescale Semiconductor

DDR Memory Controller

When the DDR memory controller operates in open page mode, it retains the currently active

SDRAM page by not issuing a precharge command. The page remains opens until one of the

following conditions occurs:

•

Refresh interval is met

•

The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.

•

There is a logical bank row collision with another transaction that must be issued.

Page mode can dramatically reduce access latencies for page hits. Depending on the memory

system design and timing parameters, using page mode can save two to three clock cycles for

subsequent burst accesses that hit in an active page. Also, better performance can be obtained by

using more banks, especially in systems which use many different channels. Page mode is disabled

by clearing DDR_SDRAM_INTERVAL[BSTOPRE] and CS_n_CONFIG[AP_n_EN]

9.5.11 Error Checking and Correcting (ECC)

The DDR memory controller supports error checking and correcting (ECC) for the data path

between the core master and system memory. The memory detects all double-bit errors, detects all

multi-bit errors within a nibble, and corrects all single-bit errors. Other errors may be detected, but

are not guaranteed to be corrected or detected. Multiple-bit errors are always reported when error

reporting is enabled. When a single-bit error occurs, the single-bit error counter register is

incremented, and its value compared to the single-bit error trigger register. An error is reported

when these values are equal. The single-bit error registers can be programmed such that minor

memory faults are corrected and ignored, but a catastrophic memory failure generates an interrupt.

For writes that are smaller than 64 bits, the DDR memory controller performs a double-word read

from system memory of the address for the write (checking for errors), and merges the write data

with the data read from memory. Then, a new ECC code is generated for the merged double word.

The data and ECC code is then written to memory. If a multi-bit error is detected on the read, the

transaction completes the read-modify-write to keep the DDR memory controller from hanging.

This read-modify-write operation is performed as an atomic transaction in the DDR controller. The

write command is then issued 3–5 memory clocks after the completion of the read, depending on

various system parameters. However, the corrupt data is masked on the write, so the original

contents in SDRAM remain unchanged. The syndrome encodings for the ECC code are shown in

Table 9-32 and Table 9-33.

Table 9-32. DDR SDRAM ECC Syndrome Encoding

Data

Bit

Syndrome Bit

Data

Bit

Syndrome Bit

012

3456

0123

4567

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