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MPC8540 Datasheet(PDF) 398 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 398 Page - Freescale Semiconductor, Inc |
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398 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 9-44 Freescale Semiconductor DDR Memory Controller 9.5.8.2.1 Self-Refresh in Sleep Mode The entry and exit timing for self-refreshing SDRAMs is shown in Figure 9-35 and Figure 9-36. Figure 9-35. DDR SDRAM Self-Refresh Entry Timing Figure 9-36. DDR SDRAM Self-Refresh Exit Timing SDRAM Clock MCS MCAS MA[13:0] MDQ[0:63] MWE MRAS MDQS (High Impedance) CKE 01 2 345 67 8910 11 12 (High Impedance) 200 Cycles SDRAM Clock MCS MCAS MA[13:0] MDQ[0:63] MWE MRAS MDQS 01 2 345 67 202 203 204 205 206 |
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