MPC8540 datasheet(394/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-40

Freescale Semiconductor

DDR Memory Controller

Figure 9-31. Registered DDR SDRAM DIMM Burst Write Timing

9.5.7

DDR SDRAM Write Timing Adjustments

The DDR memory controller facilitates system design flexibility by providing a write timing

adjustment parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and

DQS. The DDR SDRAM specification requires DQS be received no sooner than 75% of an

SDRAM clock period—and no later than 125% of a clock period—from the capturing clock edge

of the command/address at the SDRAM. The WR_DATA_DELAY parameter may be used to meet

this timing requirement for a variety of system configurations, ranging from a system with one

DIMM to a fully populated system with two DIMMS. TIMING_CFG_2[WR_DATA_DELAY]

specifies how much to delay the launching of DQS and data from the first clock edge occurring

one SDRAM clock cycle after the command is launched. The delay increment step sizes are in

1/4th SDRAM clock periods starting with the default value of 1/4th period delay. Figure 9-32

shows the use of the WR_DATA_DELAY parameter.

ACTTORW

ROW

COL

SDRAM Clock

MCS

MCAS

MA[13:0]

MDQ[0:63]

MWE

MRAS

MDQS

MDM[0:7]

COL

D1 D2 D3

D1 D2

345

8910

MPC8540 Datasheet(PDF) 394 Page - Freescale Semiconductor, Inc