MPC8540 datasheet(393/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

PDF	1302 Pages

Scroll/Zoom	100%

Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

Logo

393 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-39

Figure 9-30. DDR SDRAM Mode-Set Command Timing

9.5.6

DDR SDRAM Registered DIMM Mode

To reduce loading, registered DIMMs latch the DDR SDRAM control signals internally before

using them to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay

on the DIMMs’ control bus by delaying the data and data mask writes (on SDRAM buses) by an

extra SDRAM clock cycle.

Enabling registered DIMM mode does not affect bus timing for DDR reads. However to

compensate for latch delay on the registered DIMMs’ control signals, the programmed SDRAM

read latency value (TIMING_CFG_1[CASLAT]) must be one greater than the value needed for

non-registered DIMMs. Figure 9-31 shows the registered DDR SDRAM DIMM back-to-back

burst write timing.

Code

SDRAM Clock

MCS

MCAS

MA[0:14]

MDQ[0:63]

MWE

MRAS

MDQS

0x1

0x0

MBA[0:1]

2345

8910

MPC8540 Datasheet(PDF) 393 Page - Freescale Semiconductor, Inc