MPC8540 datasheet(399/1302 Pages) FREESCALE

399 / 1302 page

Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

9-45

9.5.9

DDR Data Beat Ordering

Transfers to and from memory are always performed in four-beat bursts (four beats = 32 bytes).

For transfer sizes other than four beats, the data transfers are still operated as four-beat bursts. If

ECC is enabled for a sub-doubleword write transaction, a full read-modify-write is performed to

properly update ECC bits. If ECC is disabled then no read-modify-write is required for

sub-doubleword writes, and the data masks (MDM[0:8]) are used to prevent writing unwanted

data to SDRAM. The DDR memory controller also uses data masks to prevent all unintended full

double words from writing to SDRAM. For example, if a write transaction is desired with a size

of one double word (8 bytes), then the 2

nd, 3rd, and 4th beats of data are not written to DRAM.

Table 9-31 lists the data beat sequencing to and from the DDR SDRAM and the data queues for

each of the possible transfer sizes with each of the possible starting double-word offsets. All

underlined double-word offsets are valid for the transaction.

9.5.10 Page Mode and Logical Bank Retention

The DDR memory controller supports an open/closed page mode with an allowable open page for

each logical bank of DRAM used. In closed page mode, the DDR memory controller uses the

SDRAM AUTO PRECHARGE feature, which allows the controller to indicate that the page must

be automatically closed by the DDR SDRAM after the READ or WRITE access. This is

performed by using MA[10] of the address during the COMMAND phase of the access to enable

AUTO PRECHARGE. AUTO PRECHARGE is non-persistent in that it is either enabled or

disabled for each individual READ or WRITE command. It can however, be enabled or disabled

separately for each chip select.

Table 9-31. Memory Controller–Data Beat Ordering

Transfer Size

Starting Double-Word

Offset

Double-Word Sequence1 to/from DRAM and Queues

1 All underlined double-word offsets are valid for the transaction.

1 double word

0 - 1 - 2 - 3

1 - 2 - 3 - 0

2 - 3 - 0 - 1

3 - 0 - 1 - 2

2 double words

0 - 1 - 2 - 3

1 - 2 - 3 - 0

2 - 3 - 0 - 1

3 double words

0 - 1 - 2 - 3

1 - 2 - 3 - 0

4 double words

0 - 1 - 2 - 3

1 - 2 - 3 - 0

2 - 3 - 0 - 1

3 - 0 - 1 - 2

MPC8540 Datasheet(PDF) 399 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 399 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL