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MPC8540 Datasheet(PDF) 403 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 403 Page - Freescale Semiconductor, Inc |
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403 / 1302 page  Initialization/Application Information MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 9-49 9.6 Initialization/Application Information System software must configure the DDR memory controller, using a memory polling algorithm at system start-up, to correctly map the size of each bank in memory. Then, the DDR memory controller uses its bank map to assert the appropriate MCS[0:3] signal for memory accesses according to the provided bank depths. System software must also configure the DDR memory controller at system start-up to multiplex appropriately the row and column address bits for each bank. Refer to row-address configuration in Section 9.4.1.2, “Chip Select Configuration (CSn_CONFIG).” Address multiplexing occurs according to these configuration bits. At system reset, initialization software (bootcode) must set up the programmable parameters in the memory interface configuration registers (MICRs). See Section 9.4.1, “Register Descriptions,” for more detailed descriptions of the configuration registers. These parameters are shown in Table 9-35. Table 9-34. Memory Controller Errors Category Error Descriptions Action Detect Register Notification Single-bit ECC threshold The number of ECC errors has reached the threshold specified in the ERR_SBE. The error is reported through an interrupt if enabled The error control register only logs read versus write, not full type. Access error Multi-bit ECC error A multi-bit ECC error is detected during a read, or read-modify-write memory operation. Memory select error Read, or write, address does not fall within the address range of any of the memory banks. Table 9-35. Memory Interface Configuration Register Initialization Parameters Name Description Parameter Section/Pag e CSn_BNDS Chip select memory bounds SAn EAn 9.4.1.1/9-10 CSn_CONFIG Chip select configuration CS_n_EN ROW_BITS_CS_n COL_BITS_CS_n 9.4.1.2/9-10 TIMING_CFG_1 DDR SDRAM timing configuration PRETOACT ACTTOPRE ACTTORW CASLAT REFREC WRREC ACTTOACT WRTORD WR_DATA_DELAY 9.4.1.3/9-11 |
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