MPC8540 datasheet(405/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-1

Chapter 10

Programmable Interrupt Controller

This chapter describes the programmable interrupt controller (PIC) interrupt protocol, various

types of interrupt sources controlled by the PIC unit, and the PIC registers with some programming

guidelines.

10.1 Introduction

A block diagram of portions of the MPC8540 showing the relationship of the various functional

blocks and external signals to the PIC unit is shown in Figure 10-1.

The PIC unit receives interrupt signals from the following sources:

•

External interrupts. Triggered by signals external to the integrated device, namely

IRQ[0:11]

•

Internal interrupts. Triggered by signal internal to the integrated device, typically

representing major blocks by from the L2 cache, the ECM, the DDR controller, the local

bus controller (LBC), the 4-channel DMA controller, the PCI/PCI-X block, the RapidIO

interface, the dual three-speed Ethernet controllers (TSECs), the 10/100 Ethernet

controller, the DUART, the performance monitor, and the I

2C controller.

•

Interrupts generated from within the PIC itself. Names the messaging, global timer, and

interprocessor interrupts defined by the OpenPIC specification

The PIC can be configured such that interrupts can be directed as follows:

•

To the core through the external interrupt signal, int. For interrupts signalled through the int

signal, the PIC unit prioritizes and manages interrupts such that the highest priority

interrupt is always recognized and taken, and that any lower priority interrupt that is

deferred when a higher priority interrupt is taken, resumes execution as soon as all higher

priority interrupts have been handled.

•

To the core through the critical interrupt signal, cint

•

To an external interrupt controller, through the IRQ_OUT signal

MPC8540 Datasheet(PDF) 405 Page - Freescale Semiconductor, Inc