MPC8540 datasheet(408/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-4

Freescale Semiconductor

Programmable Interrupt Controller

•

Four 32-bit messaging interrupt channels

•

Four global high resolution timers that can be clocked with the CCB (platform) clock or the

RTC input.

•

Fully-nested interrupt delivery

•

Processor initialization control

•

Programmable resetting of the PIC unit through the global configuration register

•

16 programmable interrupt priority levels

•

Support for connection of external interrupt controller device such as an 8259

programmable interrupt controller

•

In 8259 mode, it generates a local (internal) interrupt output signal, IRQ_OUT.

•

Recovery from spurious interrupts

10.1.3 Interrupts to the Processor Core

The int signal, which causes the external interrupt exception, is the main interrupt output from the

PIC unit to the processor core. External, internal, and message interrupts can alternately be

configured as critical interrupts (in the destination registers); these are reported to the core through

the cint signal and do not use the PIC logic described in Section 10.4.1, “Flow of Interrupt

Control.”

The Book E architecture implemented by the e500 core defines a separate critical interrupt type

with its own save and restore registers (CSRR0 and CSRR1) and return instruction (Return from

Critical Interrupt, rfci). In addition to the external and critical interrupts that are generated by the

PIC, other MPC8540 conditions (shown in Table 10-2) cause interrupts to the core (and wake up

the core when it is in a low-power state).

Table 10-2. Processor Interrupts Generated Outside the Core—Types and

Sources

Core

Interrupt Type

Signaled by

(Input to Core)

Sources

PIC-Programmable Interrupts

External

interrupt

int

Generated by the PIC, as described in Section 10.1.5, “Interrupt Sources.”

Critical interrupt

cint

Generated by the PIC, as described in Section 10.1.5, “Interrupt Sources.”

Other Interrupts Generated Outside the Core

Machine check

core_mcp

(MPC8540

causes)

• MCP

• SRESET

• Assertion of core_mcp by global utilities block

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