MPC8540 datasheet(409/1302 Pages) FREESCALE

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Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-5

The global utilities block monitors two additional interrupt conditions generated by the e500 core

(core_tbint and core_fault_out signals), as shown in Figure 10-1. Assertion of either of these

signals causes the processor to exit a low-power state. These cases are caused by core conditions,

and after the global utilities logic wakes up the core, they are handled by the core as shown in

Table 10-3.

10.1.4 Modes of Operation

Mixed or pass-through mode can be chosen by setting or clearing GCR[M] as described in

Section 10.3.1.2, “Global Configuration Register (GCR).”

10.1.4.1 Mixed Mode (GCR[M] = 1)

In mixed mode, the external and internal interrupts are delivered using the normal priority and

delivery mechanisms detailed in Section 10.3.6.1, “External Interrupt Vector/Priority Registers

(EIVPR0–EIVPR11),” through Section 10.3.6.4, “Internal Interrupt Destination Registers

(IIDR0–IIDR31).”

Unconditional

debug event

core_ude

UDE. Asserting UDE generates an unconditional debug exception type debug

interrupt and sets a bit in the debug status register, DBSR[UDE], as described in

Section 6.13.2, “Debug Status Register (DBSR).”

Reset

core_hreset

• HRESET assertion (and negation)

• core_hreset_req. Output from core—caused by writing to the core DBCR0[RST].

This condition is additionally qualified with MSR[DE] and DBCR0[IDM] bits.

Note that assertion of this signal causes a hard reset of the core only.

• core_hreset_req can also be caused by a second timer timeout condition as

described in Section 6.6.1, “Timer Control Register (TCR).”

• core_reset. Output from PIC. See Section 10.3.1.4, “Processor Initialization

Table 10-3. e500 Core-Generated Interrupts that Cause a Wake-up

Core

Interrupt

Type

Signaled by

(Output from

Core)

Sources

Fixed interval

timer

core_tbint

The source of both of these interrupts is the time base facility within the e500 core.

The MPC8540 monitors this core output signal and considers it a processor

interrupt for the purposes of power management (causes the core to exit a

low-power state). For more information about the interaction between

core-generated signals and power management, see Chapter 18, “Global Utilities.”

Decrementer

Machine

check

core_fault_out

Occurs when the L1 cache has a parity error on a snoop push operation, which can

occur while the core is halted. The MPC8540 monitors this signal and considers it

a processor interrupt for the purposes of power management (causes the core to

exit a low-power state).

Table 10-2. Processor Interrupts Generated Outside the Core—Types and

Sources (continued)

Core

Interrupt Type

Signaled by

(Input to Core)

Sources

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