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MPC8540 Datasheet(PDF) 406 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 406 Page - Freescale Semiconductor, Inc |
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406 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 10-2 Freescale Semiconductor Programmable Interrupt Controller Table 10-1 shows which signalling mechanisms are available to each interrupt source. Note that the PIC can be disabled, in which case internal interrupts are passed through IRQ_OUT. All other interrupts are disabled. 10.1.1 Overview The PIC is compliant with the OpenPIC architecture. The interrupt controller provides interrupt management, and is responsible for receiving hardware-generated interrupts from different sources (both internal and external), prioritizing them, and delivering them to the CPU for servicing. Table 10-1. Interrupt Source Signalling Options Source in t cin t IRQ_OU T Internal √√ √ External √√ √ Message √√ √ Interprocessor √ xx Global timer √ xx |
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