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MPC8540 Datasheet(PDF) 410 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 410 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
10-6
Freescale Semiconductor
Programmable Interrupt Controller
10.1.4.2 Pass-Through Mode (GCR[M] = 0)
The PIC unit provides a mechanism to support alternate external interrupt controllers such as the
PC/AT compatible 8259 interrupt controller architecture. After a hard reset, the PIC unit defaults
to pass-through mode, in which active-high interrupts from external source IRQ0 are passed
directly to the e500 core, as shown in Table 10-2, all other external interrupt signals are ignored.
Thus, the interrupt signal from an external interrupt controller can be connected to IRQ0 and cause
direct interrupts to the processor. The PIC does not perform a vector fetch from an 8259 interrupt
controller.
Figure 10-2. Pass-Through Mode Example
When pass-through mode is enabled, the internally-generated interrupts shown in Table 10-4 are
not forwarded to the e500 core. Instead, the PIC passes the raw interrupts from the internal sources
to IRQ_OUT.
Note that in pass-through mode, interrupts generated by the PIC itself (global timers,
interprocessor, and message register interrupts) cannot be used. If internal or PIC-generated
interrupts must be reported internally to the processor, pass-through mode must be disabled.
10.1.5 Interrupt Sources
Aside from the sources of machine check, unconditional debug event, and reset interrupts to the
core described in Table 10-2, the PIC unit can receive 47 separate interrupts from five different
sources as follows:
•
12 external—Off-chip signals, IRQ[0:11]
•
23 internal—On-chip. Sources are L2, ECM, DDR, local bus controller, DMA, PCI/PCI-X,
RapidIO, TSEC, FEC, DUART, performance monitor, and I
2C
•
4 global timers—From inside the PIC
IRQ_OUT
MPC8540 Internal
interrupts (see Table 10-4)
(not including
PIC-generated interrupts)
PIC
e500 Core
IRQ0
External
PC/AT-Compatible
8259 Interrupt
Controller
MPC8540
GCR[M] = 0
IRQ[1:11]
(Disabled)
int



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