MPC8540 datasheet(407/1302 Pages) FREESCALE

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Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-3

Figure 10-1. MPC8540 Interrupt Sources Block Diagram

10.1.2 Features

•

Programming model compliant with the OpenPIC architecture

•

Support for 12 external and 23 internal interrupt sources. Serial interrupts are not

supported.

•

Four interprocessor interrupt channels

PIC

Global

Timer (4)

Inter-

Processor (4)

IRQ_OUT

IRQ[0:8]

DMA_DREQ3/IRQ9

DMA_DACK3/IRQ10

DMA_DDONE3/IRQ11

External

Interrupts

cint

int

Wake up core/

interrupts

CKSTP_IN

CKSTP_OUT

HRESET

HRESET_REQ

SRESET

MCP

UDE

service interrupt

e500 Core

Timer

Facility

Watchdog

Timer

PIR[P0]

PIC-defined

Messaging

(4)

Internal Interrupts

L2 cache

e500 coherency model (ECM)

DDR DRAM

Local bus controller (LBC)

DMA channels 0–3

PCI/PCI-X

RapidIO inbound port write/ error interrupt

RapidIO doorbell inbound interrupt

RapidIO outbound message interrupt

RapidIO inbound message interrupt

TSEC 1/2 transmit interrupts

TSEC 1/2 receive interrupts

TSEC 1/2 receive/transmit error interrupts

Fast Ethernet controller (FEC)

DUART

I2C controller

Performance monitor interrupt

Global Utilities

core_reset

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