MPC8540 datasheet(404/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-50

Freescale Semiconductor

DDR Memory Controller

9.6.1

DDR SDRAM Initialization Sequence

After configuration of all parameters is complete, system software must set

DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 200

µs must elapse

after the memory clocks are stable (that is, the DLL has locked or initialization is complete of all

clock related configuration registers) before MEM_EN can be set, so a delay loop in the

initialization code may be necessary if software is enabling the memory controller. After

MEM_EN has been set, the DDR memory controller automatically performs the

JEDEC-compliant initialization sequence to initialize memories according to the information in

the SDMODE and ESDMODE fields of the DDR_SDRAM_MODE register. The initialization

sequence is as follows:

1. PRECHARGE ALL

2. MODE REGISTER SET for extended mode register

3. MODE REGISTER SET for mode register

4. PRECHARGE ALL

5. Two AUTO REFRESH commands

6. MODE REGISTER SET for mode register with reset DLL bit deactivated

Note that the BA0 and BA1 bits are automatically driven appropriately during the MODE

ready for access and the memory controller begins processing memory transactions as they arrive.

DDR_SDRAM_CFG

DDR SDRAM control configuration

SREN

ECC_EN

RD_EN

SDRAM_TYPE

DYN_PWR

9.4.1.5/9-14

DDR_SDRAM_MODE

DDR SDRAM mode configuration

ESDMODE

SDMODE

9.4.1.6/9-16

DDR_SDRAM_INTERVAL DDR SDRAM interval configuration

REFINT

BSTOPRE

9.4.1.7/9-16

Table 9-35. Memory Interface Configuration Register Initialization Parameters (continued)

Name

Description

Parameter

Section/Pag

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