MPC8540 datasheet(402/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

9-48

Freescale Semiconductor

DDR Memory Controller

9.5.12 Error Management

The DDR memory controller detects three different kinds of errors: single-bit, multi-bit, and

memory select errors. The following discussion assumes all the relevant error detection,

correction, and reporting functions are enabled as described in Section 9.4.1.16, “Memory Error

Interrupt Enable (ERR_INT_EN),” Section 9.4.1.15, “Memory Error Disable (ERR_DISABLE),”

and Section 9.4.1.14, “Memory Error Detect (ERR_DETECT).”

Single-bit errors are counted and reported based on the ERR_SBE value. When a single-bit error

is detected, the DDR memory controller does the following:

•

Corrects the data

•

Increments the single-bit error counter ERR_SBE[SBEC]

•

Generates an interrupt if the counter value ERR_SBE[SBEC] equals the programmable

threshold ERR_SBE[SBET]

•

Completes the transaction normally

If a multi-bit error is detected for a read, the DDR memory controller logs the error and generates

an interrupt (if enabled, as described in Section 9.4.1.15, “Memory Error Disable

(ERR_DISABLE)”). The final error the DDR memory controller detects is a memory select error,

which causes the DDR memory controller to log the error and generate an interrupt (if enabled, as

described in Section 9.4.1.14, “Memory Error Detect (ERR_DETECT)”). This error is detected if

the address from the memory request does not fall into any of the enabled, programmed chip select

address ranges. Table 9-34 shows the errors with their descriptions.

Table 9-33. DDR SDRAM ECC Syndrome Encoding (Check Bits)

Check

Bit

Syndrome Bit

0123

4567

•

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