MPC8540 datasheet(411/1302 Pages) FREESCALE

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Introduction

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-7

•

4 inter-processor (IPI)—Intended for communication between different processor cores on

the same device. Used only for self-interrupt in a single-core device such as the MPC8540

•

4 message registers—From inside the PIC. Triggered on register write, cleared on read.

Used for inter-process communication

10.1.5.1 Interrupt Routing—Mixed Mode

When the PIC receives an internal or external interrupt, its destination register is checked to

determine if it should be routed off-chip to the external IRQ_OUT signal (if the incoming interrupt

has its xIDR[EP] bit set). Alternatively, if the incoming interrupt has been configured in xIDR[CI]

as a critical interrupt, the PIC completes its processing of the interrupt by asserting the cint input

to the core, causing it to be serviced as a critical interrupt. As a third alternative (if neither

xIDR[CI] or xIDR[EP] are set), the interrupt can be serviced as a normal external interrupt by the

processor core (through the int signal). In this case, the interrupt is latched by the interrupt pending

followed.

10.1.5.2 Internal Interrupt Sources

Table 10-4 shows the assignments of the 23 internal interrupt sources for the MPC8540. Note that

this list does not include the interrupts generated by the PIC unit.

Table 10-4. Internal Interrupt Assignments

Internal

Interrupt

Number

Interrupt Source

Internal

Interrupt

Number

Interrupt Source

L2 cache

TSEC 1 receive interrupt

ECM

15–17

Reserved

DDR DRAM

TSEC 1 receive/transmit error interrupt

LBC

TSEC 2 transmit interrupt

DMA channel 0

TSEC 2 receive interrupt

DMA channel 1

21–23

Reserved

DMA channel 2

TSEC 2 receive/transmit error interrupt

DMA channel 3

Fast Ethernet controller (FEC)

PCI/PCI-X

DUART

RapidIO inbound port write/ error interrupt

I2C controller

RapidIO doorbell inbound interrupt

Performance monitor interrupt

RapidIO outbound message interrupt

Unused

RapidIO inbound message interrupt

Unused

TSEC 1 transmit interrupt

Unused

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