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MPC8540 Datasheet(PDF) 415 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 415 Page - Freescale Semiconductor, Inc |
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415 / 1302 page  Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 10-11 0x4_1120 GTVPR0—Global timer 0 vector/priority register R/W 0x8000_0000 10.3.2.4/10-22 0x4_1130 GTDR0—Global timer 0 destination register R/W 0x0000_0001 10.3.2.5/10-23 0x4_1140 GTCCR1—Global timer 1 current count register R 0x0000_0000 10.3.2.2/10-21 0x4_1150 GTBCR1—Global timer 1 base count register R/W 0x8000_0000 10.3.2.3/10-21 0x4_1160 GTVPR1—Global timer 1 vector/priority register R/W 0x8000_0000 10.3.2.4/10-22 0x4_1170 GTDR1—Global timer 1 destination register R/W 0x0000_0001 10.3.2.5/10-23 0x4_1180 GTCCR2—Global timer 2 current count register R 0x0000_0000 10.3.2.2/10-21 0x4_1190 GTBCR2—Global timer 2 base count register R/W 0x8000_0000 10.3.2.3/10-21 0x4_11A0 GTVPR2—Global timer 2 vector/priority register R/W 0x8000_0000 10.3.2.4/10-22 0x4_11B0 GTDR2—Global timer 2 destination register R/W 0x0000_0001 10.3.2.5/10-23 0x4_11C0 GTCCR3—Global timer 3 current count register R 0x0000_0000 10.3.2.2/10-21 0x4_11D0 GTBCR3—Global timer 3 base count register R/W 0x8000_0000 10.3.2.3/10-21 0x4_11E0 GTVPR3—Global timer 3 vector/priority register R/W 0x8000_0000 10.3.2.4/10-22 0x4_11F0 GTDR3—Global timer 3 destination register R/W 0x0000_0001 10.3.2.5/10-23 0x4_1200– 0x4_12F0 Reserved — — — 0x4_1300 TCR—Timer control register R/W 0x0000_0000 10.3.2.6/10-24 0x4_1310 IRQSR0—IRQ_OUT summary register 0 R 0x0000_0000 10.3.3.1/10-26 0x4_1320 IRQSR1—IRQ_OUT summary register 1 R 0x0000_0000 10.3.3.2/10-27 0x4_1330 CISR0—Critical Interrupt summary register 0 R 0x0000_0000 10.3.3.3/10-27 0x4_1340 CISR1—Critical Interrupt summary register 1 R 0x0000_0000 10.3.3.4/10-28 0x4_1350 PM0MR0—Performance monitor 0 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_1360 PM0MR1—Performance monitor 0 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_1370 PM1MR0—Performance monitor 1 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_1380 PM1MR1—Performance monitor 1 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_1390 PM2MR0—Performance monitor 2 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_13A0 PM2MR1—Performance monitor 2 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_13B0 PM3MR0—Performance monitor 3 mask register 0 R/W 0x00FF_FFFF 10.3.4.1/10-29 0x4_13C0 PM3MR1—Performance monitor 3 mask register 1 R/W 0xFFFF_FFFF 10.3.4.2/10-30 0x4_13D0– 0x4_13F0 Reserved — — — Table 10-7. PIC Register Address Map (continued) Offset Register Access Reset Section/Page |
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