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MPC8540 Datasheet(PDF) 419 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 419 Page - Freescale Semiconductor, Inc |
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419 / 1302 page  Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 10-15 0x5_05B0 IIDR29—Internal interrupt 29 destination register R/W 0x0000_0001 10.3.6.4/10-35 0x5_05C0 IIVPR30—Internal interrupt 30 vector/priority register R/W 0x8080_0000 10.3.6.3/10-34 0x5_05D0 IIDR30—Internal interrupt 30 destination register R/W 0x0000_0001 10.3.6.4/10-35 0x5_05E0 IIVPR31—Internal interrupt 31 vector/priority register R/W 0x8080_0000 10.3.6.3/10-34 0x5_05F0 IIDR31—Internal interrupt 31 destination register R/W 0x0000_0001 10.3.6.4/10-35 0x5_0600– 0x5_15F0 Reserved — — — 0x5_1600 MIVPR0—Messaging interrupt 0 (MSG 0) vector/priority register R/W 0x8000_0000 10.3.6.5/10-36 0x5_1610 MIDR0—Messaging interrupt 0 (MSG 0) destination register R/W 0x0000_0001 10.3.6.6/10-37 0x5_1620 MIVPR1—Messaging interrupt 1 (MSG 1) vector/priority register R/W 0x8000_0000 10.3.6.5/10-36 0x5_1630 MIDR1—Messaging interrupt 1 (MSG 1) destination register R/W 0x0000_0001 10.3.6.6/10-37 0x5_1640 MIVPR2—Messaging interrupt 2 (MSG 2) vector/priority register R/W 0x8000_0000 10.3.6.5/10-36 0x5_1650 MIDR2—Messaging interrupt 2 (MSG 2) destination register R/W 0x0000_0001 10.3.6.6/10-37 0x5_1660 MIVPR3—Messaging interrupt 3 (MSG 3) vector/priority register R/W 0x8000_0000 10.3.6.5/10-36 0x5_1670 MIDR3—Messaging interrupt 3 (MSG 3) destination register R/W 0x0000_0001 10.3.6.6/10-37 0x5_1680– 0x5_FFF0 Reserved — — — PIC Register Address Map—Per-CPU Registers 0x6_0000– 0x6_0030 Reserved — — — 0x6_0040 IPIDR0—P0 IPI 0 dispatch register W All zeros 10.3.7.1/10-39 0x6_0050 IPIDR1—P0 IPI 1 dispatch register 0x6_0060 IPIDR2—P0 IPI 2 dispatch register 0x6_0070 IPIDR3—P0 IPI 3 dispatch register 0x6_0080 CTPR0—P0 current task priority register R/W 0x0000_000F 10.3.7.2/10-40 0x6_0090 WHOAMI0—P0 who am I register R All zeros 10.3.7.3/10-41 0x6_00A0 IACK0—P0 interrupt acknowledge register R All zeros 10.3.7.4/10-41 0x6_00B0 EOI0—P0 end of interrupt register W All zeros 10.3.7.5/10-42 1 Note that these registers provider private access space to the same set of registers at offset 0x6_xxxx. This private access is described in Section 10.3.7, “Per-CPU Registers.” Table 10-7. PIC Register Address Map (continued) Offset Register Access Reset Section/Page |
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