MPC8540 datasheet(421/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-17

10.3.1.2 Global Configuration Register (GCR)

The global configuration register (GCR) shown in Figure 10-4 controls the PIC’s operating mode,

and allows software to reset the PIC.

Figure 10-4. Global Configuration Register (GCR)

Table 10-9 describes the GCR fields.

10.3.1.3 Vendor Identification Register (VIR)

The vendor identification register (VIR) shown in Figure 10-5 has specific read-only information

about the vendor and the device revision.

Figure 10-5. Vendor Identification Register (VIR)

RST

0000

00000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1020

Table 10-9. GCR Field Descriptions

Bits

Name

Description

RST

Reset. Setting this field forces the PIC to be reset. Cleared automatically when the reset sequence

is complete. SeeSection 10.4.7, “Reset of the PIC,” for more information on resetting the PIC.

—

Reserved

Mode. PIC operating mode.

0 Pass-through mode. On-chip PIC is disabled and interrupts detected on IRQ0 are passed directly

to the processor core. See Section 10.1.4, “Modes of Operation,” for more details.

1 Mixed mode. Interrupts are handled by the normal priority and delivery mechanisms of the PIC.

See Section 10.1.4, “Modes of Operation,” for more details.

3–31

—

Reserved

15 1623 2431

R 0

0000000

STEP

DEVICE ID

VENDOR ID

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1080

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