MPC8540 datasheet(425/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-21

Table 10-14 describes the TFRR register.

10.3.2.2 Global Timer Current Count Registers (GTCCRn)

The global timer current count registers (GTCCRs), shown in Figure 10-10, contain the current

count for each of the four PIC timers.

Figure 10-10. Global Timer Current Count Registers (GTCCRn)

Table 10-15 describes the GTCCRn fields.

10.3.2.3 Global Timer Base Count Registers (GTBCRn)

The global timer base count registers (GTBCRn) contain the base counts for each of the four PIC

timers as shown in Figure 10-11. This value is reloaded into the corresponding GTCCRn when the

current count reaches zero. Note that when zero is written to the base count field, (and

GTCCRn[CI] = 0), the timer generates an interrupt on every timer cycle.

Table 10-14. TFRR Field Descriptions

Bits

Name

Description

0–31

FREQ Timer frequency (in ticks/second (Hz)). Used to communicate the frequency of the global timers’ clock

source (the core complex bus (CCB) clock) to user software. See Section 4.4.4, “Clocking,” for more

details. TFRR is set only by software for later use by other applications and its value in no way affects

the operating frequency of the global timers. The timers operate at a ratio of this clock frequency set by

TCR[CLKR]. See Section 10.3.2.6, “Timer Control Register (TCR).”

R TOG

COUNT

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1100, 0x4_1140, 0x4_1180, 0x4_11C0

Table 10-15. GTCCRn Field Descriptions

Bits

Name

Description

TOG

Toggle. Toggles when the current count decrements to zero. Cleared when GTBCRn[CI] goes from 1 to 0.

1–31

COUN

Current count. Decremented while GTBCRn[CI] is zero. When the timer count reaches zero, an interrupt

is generated (provided it is not masked), the toggle bit is inverted, and the count is reloaded. For

non-cascaded timers, the reload value is the contents of the corresponding base count register. Cascaded

timers are reloaded with either all ones, or the contents of the base count register, depending on the value

of TCR[ROVR]. See Section 10.3.2.6, “Timer Control Register (TCR),” for more details.

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