MPC8540 datasheet(428/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-24

Freescale Semiconductor

Programmable Interrupt Controller

10.3.2.6 Timer Control Register (TCR)

The timer control register (TCR) shown in Figure 10-15 provides various configuration options

such as count frequency and roll-over behavior.

There are two choices for the clock source for the timers: a selectable frequency ratio from the

CCB clock, or the RTC signal. The TCR also provides the ability to create timers larger than the

default 31-bit global timers. Timer cascade fields allow configuration of up to two 63-bit timers,

one 95-bit timer or one 127-bit timer.

With one exception mentioned below, the value reloaded into a timer is determined by its roll-over

control field TCR[ROVR]. Setting a timer’s roll-over field causes its current count register to roll

over to all ones when the count reaches zero. This is equivalent to reloading the count register with

0xFFFF_FFFF instead of its base count value. Clearing a timer’s associated ROVR bit ensures the

timer always reloads with its base count value.

When timers are cascaded the last (most significant) counter in the cascade also affects their

roll-over behavior. Cascaded timers always reload their base count when the most significant

counter has decremented to zero, regardless of the settings in TCR[ROVR].

For example, timers 0, 1, and 2 can be cascaded to generate one interrupt every hour. As shown in

Table 10-19, given a CCB clock of 333 MHz, letting the timer clock frequency default to 1/8 the

system clock, (TCR[CLKR] = 0 sets a clock ratio of 8), provides a basic input of 41.625 MHz to

timer 0. Setting timer 0 to count 41,625,000 (0x27B_25A8) timer clock cycles will generate one

output per second. Setting both timers 1 and 2 to 59, and cascading all three timers, generates one

interrupt every hour from timer 2.

Figure 10-14. Example Calculation for Cascaded Timers

Figure 10-15. Timer Control Register (TCR)

Table 10-19. Parameters for Hourly Interrupt Timer Cascade Example

System Clock

Clock Ratio

Timer Clock

Timer 0 Count

Timer 1 Count

Timer 2 Count

333 MHz

1 / 8

41.625 MHz

41.625 x 106

(0x027B_25A8)

591

(0x0000_0036)

1 Counting down from 59 through 0 requires 60 ticks.

(0x0000_0036)

141516

21 22 23 24

28 29

R 000

ROVR

00000

RTM

0000

CLKR

0000

CASC

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1300

(41.625 x 106 ticks/sec) * (60 sec/min) * (60 min/hr) = total ticks/hr generating 1 interrupt/hr

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