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MPC8540 Datasheet(PDF) 432 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 432 Page - Freescale Semiconductor, Inc |
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432 / 1302 page ![]() MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 10-28 Freescale Semiconductor Programmable Interrupt Controller Table 10-23 describes the CISR0 fields. 10.3.3.4 Critical Interrupt Summary Register 1 (CISR1) Figure 10-19 shows CISR1. Figure 10-19. Critical Interrupt Summary Register 1 (CISR1) Table 10-24 describes CISR1 register. 10.3.4 Performance Monitor Mask Registers (PMMRs) There are four pairs of performance monitor mask registers, PMnMR0 and PMnMR1. Each pair can be configured to select one interrupt source (interprocessor, timer, message, external, or internal) to generate a performance monitor event. The performance monitor can be configured to track this event in the performance monitor local control registers. See Section 19.3.2.2, “Performance Monitor Local Control Registers (PMLCAn and PMLCBn).” Table 10-23. CISR0 Field Descriptions Bits Name Description 0–15 — Reserved 16–19 MSGn Message interrupts 0–3. Bit 16 represents MSG0; bit 19 represents MSG3. 0 The corresponding interrupt is not active or not directed to cint. 1 The corresponding interrupt is active and is directed to the cint (if the corresponding xIDR[CI] is set). 20–31 EXTn External interrupts 0–11. Bit 20 represents IRQ0. Bit 31 represents IRQ11. 0 The corresponding interrupt is not active or not directed to cint. 1 The corresponding interrupt is active and is directed to the cint (if the corresponding xIDR[CI] is set). 0 31 RINTn W Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset 0x4_1340 Table 10-24. CISR1 Field Descriptions Bits Name Description 0–3 1 INTn Internal interrupts 0–31. Bit 0 represents INT0. Bit 31 represents INT31. 0 Corresponding interrupt is not active or not directed to cint. 1 The corresponding interrupt is active and is directed to the cint (if the corresponding xIDR[CI] is set). |
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