MPC8540 datasheet(434/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-30

Freescale Semiconductor

Programmable Interrupt Controller

10.3.4.2 Performance Monitor Mask Registers (Upper) (PMnMR1)

Figure 10-21 shows the PM0MR1–PM3MR1 fields.

Figure 10-21. Performance Monitor Mask Registers (PMnMR1)

Table 10-26 describes the PMnMR1 registers.

10.3.5 Message Registers

Writing to one of the four message registers (MSGR0–MSGR3) causes a messaging interrupt to

the processor. Reading this register clears the messaging interrupt. Note that a messaging interrupt

can also be cleared by writing a one to the corresponding status field of the PIC message status

10.3.5.1 Message Registers (MSGR0–MSGR3)

The message registers (MSGR0–MSGR3) are shown in Table 10-22.

Figure 10-22. Message Registers (MSGRs)

Table 10-27 describes the MSGR registers.

INT

Reset

1111_1111_1111_1111_1111_1111_1111_1111

Offset

PM0MR1 0x4_1360, PM1MR1 0x4_1380, PM2MR1 0x4_13A0, PM3MR1 0x4_13C0

Table 10-26. PMnMR1 Field Descriptions

Bits

Nam

Description

0–31

INT

Internal interrupts 0–31

0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.

1 The corresponding interrupt does not generate a performance monitor event.

MSG

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

MSGR0 0x4_1400, MSGR1 0x4_1410, MSGR2 0x4_1420, MSGR3 0x4_1430

Table 10-27. MSGRn Field Descriptions

Bits

Name

Description

0–31

MSG

Message. Contains the 32-bit message data.

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