MPC8540 datasheet(437/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-33

Table 10-30 describes the EIVPR fields.

10.3.6.2 External Interrupt Destination Registers (EIDR0–EIDR11)

The external interrupt destination registers (EIDRn), shown in Figure 10-26, control the

destination of external interrupts caused by the assertion of any of IRQ[0:11]. All external

interrupts are directed to the processor 0 interrupt, int, by default. External interrupts can be

selectively directed to IRQ_OUT or to the processor 0 critical interrupt signal, cint, instead of int

by writing to the appropriate EIDRn fields.

NOTE

The behavior of the PIC unit is not defined if both the EP and CI bits

of the same interrupt destination register are set.

Figure 10-26. External Interrupt Destination Registers (EIDRn)

Table 10-30. EIVPRn Field Descriptions

Bits

Name

Description

MSK

Mask. Masks interrupts from this source.

0 If the corresponding IPR bit is set an interrupt request is generated.

1 Interrupts from this source are disabled.

Activity. A read-only field indicating that an interrupt has been requested or is in-service. Note: The

P (polarity), S (sense), VECTOR and PRIORITY values should not be changed while the

corresponding interrupt is active, that is, while EIVPRn [A] is set.

0 No current interrupt activity associated with this source.

1 The interrupt bit for this source is set in the IPR or ISR.

2–7

—

Reserved.

Polarity. Specifies the polarity for the external interrupt.

0 Polarity is active-low or negative edge triggered.

1 Polarity is active-high or positive edge-triggered.

Sense. Specifies the sense for external interrupts.

0 The external interrupt is edge sensitive.

1 The external interrupt is level-sensitive.

10–11

—

Reserved.

12–15

PRIORIT

Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A

priority level of 0 disables interrupts from this source.

16–31

VECTOR Vector. Contains the value returned when the interrupt acknowledge (IACK) register is read and

this interrupt resides in the interrupt request register (IRR) shown in Figure 10-37.

EP CI

000

000 P0

Reset

0000_0000_0000_0000_0000_0000_0000_0001

Offset EIDR0 0x5_0010, EIDR1 0x5_0030, EIDR2 0x5_0050, EIDR3 0x5_0070, EIDR4 0x5_0090, EIDR5 0x5_00B0,

EIDR6 0x5_00D0, EIDR7 0x5_00F0, EIDR8 0x5_0110, EIDR9 0x5_0130, EIDR10 0x5_0150, EIDR11 0x5_0170

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