MPC8540 datasheet(441/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-37

10.3.6.6 Messaging Interrupt Destination Registers (MIDR0–MIDR3)

The messaging interrupt destination registers (MIDRn), shown in Figure 10-30, control the

destination for the messaging interrupts. MIDR enables the user to direct the interrupt to either the

external interrupt output pin (IRQ_OUT), the core’s critical interrupt input (cint), or to its normal

interrupt input (int).

NOTE

The behavior of the PIC unit is not defined if both the EP and CI bits

of the same interrupt destination register are set.

Figure 10-30. Messaging Interrupt Destination Registers (MIDRn)

Table 10-35 describes the MIDRn fields.

12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A

priority level of 0 disables interrupts from this source.

16–31

VECTOR

Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is

read and this interrupt resides in the interrupt request register (IRR) shown in Figure 10-37.

EP CI

000

000 P0

Reset

0000_0000_0000_0000_0000_0000_0000_0001

Offset

0x5_1610, 0x5_1630, 0x5_1650, 0x5_1670

Table 10-35. MIDRn Field Descriptions

Bits

Name

Description

External pin. Allows message interrupt to be serviced externally.

0 Message interrupt is serviced internally with int signal to the processor core.

1 Message interrupt is directed to IRQ_OUT for external service. The behavior of the PIC is not defined

if both EP and CI are set on the same interrupt destination register.

Critical interrupt

0 Message interrupt is serviced internally with int signal to the processor core.

1 Message interrupt is directed to the processor 0 as a critical interrupt with the cint signal. The

behavior of the PIC is not defined if both EP and CI are set on the same interrupt destination register.

2–30

—

Reserved

Processor 0. Indicates that processor 0 handles any interrupt. This bit is meaningful only in a multi-core

device. Because the MPC8540 is a single-core device, all interrupts that are serviced internally are

always directed to processor 0. Permanently set and read only.

1 Interrupt directed to processor 0.

Table 10-34. MIVPRn Field Descriptions (continued)

Bits

Name

Description

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