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MPC8540 Datasheet(PDF) 443 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 443 Page - Freescale Semiconductor, Inc |
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443 / 1302 page  Memory Map/Register Definition MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 10-39 Figure 10-31. Per-CPU Register Address Decoding in a Four-Core Device 10.3.7.1 Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3) There are four interprocessor interrupt dispatch registers (IPIDRs), one for each IPI channel, as shown in Figure 10-32. Writing to an IPIDR with a bit set causes a self interrupt. Interprocessor interrupts are of limited usefulness in a single-core device; however, this feature can serve as a doorbell type interrupt because external bus masters can write to these registers. 0 30 31 R 0000000000000000000000000 000000 W P0 Reset 0000_0000_0000_0000_0000_0000_0000_0000 Offset IPIDR0 0x6_0040, IPIDR1 0x6_0050 IPIDR2 0x6_0060, IPIDR3 0x6_0070 (see Section 10.3.7, “Per-CPU Registers.”) Figure 10-32. Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3) Reg 3 Reg 2 Reg 1 Reg 0 ID3 ID2 ID1 ID0 Per-CPU Register Normal Register Uses Core ID Processor IACK Registers (one per core) 0x40 0x40 0x40 0x40 Address Cores Address Decode Address Decode |
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