MPC8540 datasheet(439/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-35

Table 10-32 describes the IIVPRn fields.

10.3.6.4 Internal Interrupt Destination Registers (IIDR0–IIDR31)

Internal interrupt destination registers (IIDRn), shown in Figure 10-28, have the same fields and

format as EIVDRn, except that they apply to the internal interrupt sources listed in Table 10-4.

Like external interrupts, internal interrupts can be directed only to processor 0.

NOTE

The behavior of the PIC unit is not defined if both the EP and CI bits

of the same interrupt destination register are set.

Figure 10-28. Internal Interrupt Destination Registers (IIDRn)

Table 10-32. IIVPRn Field Descriptions

Bits

Name

Description

MSK

Mask. Mask interrupts from this source.

0 An interrupt request is generated when the corresponding IPR field is set.

1 Further interrupts from this source are disabled.

Activity. Indicates an interrupt has been requested or is in-service. Note this field is read only. The

VECTOR and PRIORITY values should not be changed while IIVPRn [A] is set.

0 No current interrupt activity associated with this source.

1 The interrupt field for this source is set in the IPR or ISR.

2–7

—

Reserved

Polarity. Specifies the polarity for the internal interrupt. Note: Because all internal interrupts are

active-high, clearing this bit disables the interrupt.

0 Interrupt polarity is active-low. This value disables the interrupt.

1 Interrupt polarity is active-high. This is the reset value should not be changed.

9–11

—

Reserved.

12–15

PRIORIT

Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A

priority level of 0 disables interrupts from this source.

16–31

VECTOR Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is

read and this interrupt resides in the interrupt request register (IRR) shown in Figure 10-37.

EP CI

00 000 000 000 000 000 000 000 000 00

Reset

0000_0000_0000_0000_0000_0000_0000_0001

Offset

IIDR0–7: 0x5_0210, 0x5_0230, 0x5_0250, 0x5_0270, 0x5_0290, 0x5_02B0, 0x5_02D0, 0x5_02F0

IIDR8–15: 0x5_0310, 0x5_0330, 0x5_0350, 0x5_0370, 0x5_0390, 0x5_03B0, 0x5_03D0, 0x5_03F0

IIDR16–23: 0x5_0410, 0x5_0430, 0x5_0450, 0x5_0470, 0x5_0490, 0x5_04B0, 0x5_04D0, 0x5_04F0

IIDR24–31: 0x5_0510, 0x5_0530, 0x5_0550, 0x5_0570, 0x5_0590, 0x5_05B0, 0x5_05D0, 0x5_05F0

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