MPC8540 datasheet(435/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-31

10.3.5.2 Message Enable Register (MER)

The message enable register (MER) shown in Figure 10-23 contains the enable bits for each

message register. The enable bit must be set to enable interrupt generation when the corresponding

message register is written.

Figure 10-23. Message Enable Register (MER)

Table 10-28 describes the MER fields.

10.3.5.3 Message Status Register (MSR)

The PIC message status register (MSR) shown in Figure 10-24 contains status bits for each

message register. The status bit is set when the corresponding messaging interrupt is active.

Reading the corresponding message register or writing a 1 to a status bit clears the corresponding

message interrupt and the status bit.

Figure 10-24. Message Status Register (MSR)

27 28

R 0000

000000000

00000000

0000000

E3 E2 E1 E0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1500

Table 10-28. MER Field Descriptions

Bits

Name

Description

0–27

—

Reserved

Enable 3. Used to enable interrupt generation for MSGR3.

0 Interrupt generation for MSGR3 disabled.

1 Interrupt generation for MSGR3 enabled.

Enable 2. Used to enable interrupt generation for MSGR2.

0 Interrupt generation for MSGR2 disabled.

1 Interrupt generation for MSGR2 enabled.

Enable 1. Used to enable interrupt generation for MSGR1.

0 Interrupt generation for MSGR1 disabled.

1 Interrupt generation for MSGR1 enabled.

Enable 0. Used to enable interrupt generation for MSGR0.

0 Interrupt generation for MSGR0 disabled.

1 Interrupt generation for MSGR0 enabled.

27 28

R 0000

000000000

00000000

0000000

S3 S2 S1 S0

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1510

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