MPC8540 datasheet(431/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-27

10.3.3.2 IRQ_OUT Summary Register 1 (IRQSR1)

Figure 10-17 shows IRQSR1.

Figure 10-17. IRQ_OUT Summary Register 1 (IRQSR1)

Table 10-22 describes the IRQSR1 fields.

10.3.3.3 Critical Interrupt Summary Register 0 (CISR0)

The critical interrupt summary registers contain one bit for each interrupt source. The

corresponding bit is set if the interrupt is active and is directed to the processor’s critical interrupt

signal cint (if the CI field in its corresponding destination register is set). Figure 10-18 shows

CISR0.

Figure 10-18. Critical Interrupt Summary Register 0 (CISR0)

RINTn

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1320

Table 10-22. IRQSR1 Field Descriptions

Bits

Name

Description

0–31

INTn

Internal interrupts 0–31 status. Bit 0 represents INT0. Bit 31 represents INT31.

0 The corresponding interrupt is not active or not directed to IRQ_OUT.

1 The corresponding interrupt is active and is directed to IRQ_OUT (that is, if the corresponding

xIDR[EP] is set).

015 16

19 20

R 0000

000000

MSGn

EXTn

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1330

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