MPC8540 datasheet(433/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-29

10.3.4.1 Performance Monitor Mask Register (Lower) (PMnMR0)

Figure 10-20 shows the PMnMR0 registers. Each register is paired with a PMnMR1 register.

Because each unreserved bit in the 64-bit pair (PMnMR0/1) specifies a different interrupt, only

one bit in each pair can be unmasked at a time. Unmasking more than one bit per pair is considered

a programming error and results in unpredictable behavior.

Figure 10-20. Performance Monitor Mask Registers (PMnMR0)

Table 10-25 describes the PMnMR0 fields.

11 12

15 16

19 20

R 0

000

IPI

TIMER

MSG

EXT

Reset

0000_0000_1111_1111_1111_1111_1111_1111

Offset

PM0MR0 0x4_1350, PM1MR0 0x4_1370, PM2MR0 0x4_1390, PM3MR0 0x4_13B0

Table 10-25. PMnMR0 Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–11

IPI

IPI interrupts 0–3

0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.

1 The corresponding interrupt does not generate a performance monitor event.

12–15

TIMER Timer interrupts 0–3

0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.

1 The corresponding interrupt does not generate a performance monitor event.

16–19

MSG

Message interrupts 0–3

0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.

1 The corresponding interrupt does not generate a performance monitor event.

20–31

EXT

External interrupts IRQ[0:11]

0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.

1 The corresponding interrupt does not generate a performance monitor event.

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