MPC8540 datasheet(429/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-25

Table 10-20 describes the TCR fields.

Table 10-20. TCR Field Descriptions

Bits

Name

Description

0–4

—

Reserved

5–7

ROVR Roll-over control for cascaded timers only. Specifies behavior when count reaches zero by identifying

the source of the reload value. Cascaded timers are always reloaded with their base count value when

the more significant timer in the cascade (the upstream timer) is zero. Bits 5–7 correspond to timers

2–0. Note that global timer 3 always reloads with its base count register.

0 Timer does not roll over. When the count reaches zero, current count register is reloaded with the

base count register value.

1 Timer rolls over at zero to all ones. (When the count reaches zero, current count register is reloaded

with 0xFFFF_FFFF.)

000 All timers reload with base count.

001 Timers 1 and 2 reload with base count, timer 0 rolls over (reloads with 0xFFFF_FFFF).

010 Timers 0 and 2 reload with base count, timer 1 rolls over (reloads with 0xFFFF_FFFF).

011 Timer 2 reloads with base count, timers 0 and 1 roll over (reload with 0xFFFF_FFFF).

100 Timers 0 and 1 reload with base count, timer 2 rolls over (reloads with 0xFFFF_FFFF).

101 Timer 1 reloads with base count, timers 0 and 2 roll over (reload with 0xFFFF_FFFF).

110 Timer 0 reloads with base count, timers 1 and 2 roll over (reload with 0xFFFF_FFFF).

111 Timers 0, 1, and 2 roll over (reload with 0xFFFF_FFFF).

8–14

—

Reserved

RTM

Real time mode. Specifies the clock source for the PIC timers.

0 Timer clock frequency is a ratio of the frequency of the platform (CCB) clock as determined by the

CLKR field. This is the default value.

1 The RTC signal is used to clock the PIC timers. If this bit is set, the CLKR field has no meaning.

16–21

—

Reserved

22–23

CLKR

Clock ratio. Specifies the ratio of the timer frequency to the platform (CCB) clock. The following clock

ratios are supported:

00 Default. Divide by 8

01 Divide by 16

10 Divide by 32

11 Divide by 64

24–28

—

Reserved

29–31

CASC Cascade timers. Specifies the output of particular global timers as input to others.

000 Default. Timers not cascaded

001 Cascade timers 0 and 1

010 Cascade timers 1 and 2

011 Cascade timers 0, 1, and 2

100 Cascade timers 2 and 3

101 Cascade timers 0 and 1; timers 2 and 3

110 Cascade timers 1, 2, and 3

111 Cascade timers 0, 1, 2, and 3

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