MPC8540 datasheet(426/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-22

Freescale Semiconductor

Programmable Interrupt Controller

Figure 10-11. Global Timer Base Count Registers (GTBCRn)

Table 10-16 describes the GTBCRn fields.

10.3.2.4 Global Timer Vector/Priority Registers (GTVPRn)

The global timer vector/priority registers (GTVPRn) contain the interrupt vector and the interrupt

priority as shown in Figure 10-12. They also contain the mask and activity fields.

Figure 10-12. Global Timer Vector/Priority Registers (GTVPRn)

BASE CNT

Reset

1000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1110, 0x4_1150, 0x4_1190, 0x4_11D0

Table 10-16. GTBCRn Field Descriptions

Bits

Name

Description

Count inhibit. Always set following reset

0 Counting enabled

1 Counting inhibited

1–31

BASE

CNT

Base count. When CI transitions from 1 to 0, this value is copied into the corresponding current

count register and the toggle bit is cleared. If CI is already cleared (counting is in progress), the base

count is copied to the current count register at the next zero crossing of the current count.

1112

1516

MSK

A 0000

000000

PRIORITY

VECTOR

Reset

1000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1120, 0x4_1160, 0x4_11A0, 0x4_11E0

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