MPC8540 datasheet(422/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-18

Freescale Semiconductor

Programmable Interrupt Controller

Table 10-10 describes the VIR fields.

10.3.1.4 Processor Initialization Register (PIR)

The processor initialization register in the PIC provides a mechanism for software to reset the

processor. The core_reset signal to the processor is held active until a zero is written to the

processor initialization register field. Thus, PIR should only be written by an external host and the

external host should wait at least 100 µsec to clear this field after writing it. The processor should

not attempt to write to PIR because writing to it resets the core, and the core will not be able to

clear the reset field, and so it would remain in reset indefinitely.

Note that although the architecture was designed to support multiple processing cores, only fields

corresponding to processors on the device are implemented, as shown in Figure 10-6. In a

uniprocessor system, only PIR[P0] is implemented.

Figure 10-6. Processor Initialization Register (PIR)

Table 10-11 describes the PIR fields.

Table 10-10. VIR Field Descriptions

Bits

Name

Description

0–7

—

Reserved

8–15

STEP

Stepping. Indicates the silicon revision for this device. Has no meaning when the VENDOR ID

value is zero.

16–23

DEVICE ID Device identification. Vendor-specified identifier for this device. Has no meaning when the

VENDOR ID value is zero.

24–31

VENDOR

Vendor identification. Specifies the manufacturer of this part. A value of zero implies a generic

PIC-compliant device.

R 0000

000

0000

000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_1090

Table 10-11. PIR Field Descriptions

Bits

Name

Description

0–30

—

Reserved

Processor 0 core reset. Setting this bit causes the PIC unit to assert the core_reset signal to

processor 0 (the e500 core).

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