MPC8540 datasheet(423/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-19

10.3.1.5 IPI Vector/Priority Registers (IPIVPRn)

The interprocessor interrupt (IPI) vector/priority registers contain the interrupt vector and priority

fields for the four interprocessor interrupt channels as shown in Figure 10-7. There is one IPI

vector/priority register per channel. The VECTOR and PRIORITY values should not be changed

while IPIVPRn[A] is set.

Figure 10-7. IPI Vector/Priority Registers (IPIVPRn)

Table 10-12 describes the IPIVPRn fields.

10.3.1.6 Spurious Vector Register (SVR)

The spurious vector register (SVR) shown in Figure 10-8 contains the 16-bit vector returned to the

processor when the IACK register is read for a spurious interrupt. See Section 10.4.4, “Spurious

Vector Generation,” for more information about the events and conditions that may cause a

spurious vector fetch.

11 12

15 16

MSK

000

0000000

PRIORITY

VECTOR

Reset

1000_0000_0000_0000_0000_0000_0000_0000

Offset

0x4_10A0, 0x4_10B0, 0x4_10C0, 0x4_10D0

Table 10-12. IPIVPRn Field Descriptions

Bits

Name

Description

MSK

Mask. Mask interrupts from this source. Always set following reset.

0 An interrupt request is generated if the corresponding IPR bit is set.

1 Further interrupts from this source are disabled.

Activity. Indicates an interrupt has been reported or is in-service. Note that this field is read only.

The VECTOR and PRIORITY values should not be changed while IPIVPRn[A] is set.

0 No current interrupt activity associated with this source.

1 The interrupt bit for this source in the IPR or ISR is set.

2–11

—

Reserved

12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A

priority level of 0 disables interrupt reporting from this source.

16–31

VECTOR

Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register

is read and this interrupt resides in the interrupt request register (IRR) shown in Figure 10-37.

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