MPC8540 datasheet(427/1302 Pages) FREESCALE

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Memory Map/Register Definition

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

10-23

Table 10-17 describes the GTVPRn fields.

10.3.2.5 Global Timer Destination Registers (GTDRn)

The global timer destination register controls the destination processor for this timer’s interrupt,

as shown in Figure 10-13.

Figure 10-13. Global Timer Destination Registers (GTDRn)

Table 10-18 describes the GTDRn fields.

Table 10-17. GTVPRn Field Descriptions

Bits

Name

Description

MSK

Mask. Inhibits interrupts from this source.

0 Interrupt requests are generated when the corresponding IPR bit is set.

1 Further interrupts from this source are disabled.

Activity. This field is read-only.

0 No current interrupt activity associated with this source.

1 An interrupt has been requested by the corresponding source or is currently being serviced. The

interrupt bit for this source is set in the IPR or ISR.

The VECTOR and PRIORITY values should not be changed while the A bit is set.

2–11

—

Reserved

12–15

PRIORIT

Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A

priority level of 0 disables interrupts from this source.

16–31

VECTOR Vector. The vector value in this field is returned when the interrupt acknowledge (IACK) register is

read and this interrupt resides in the interrupt request register shown in Figure 10-37.

30 31

R 0 0

0 0

000

0 P0

Reset

0000_0000_0000_0000_0000_0000_0000_0001

Offset

0x4_1130, 0x4_1170, 0x4_11B0, 0x4_11F0

Table 10-18. GTDRn Field Descriptions

Bits

Name

Description

0–30

—

Reserved

Processor 0. Indicates that processor 0 handles any interrupt. This bit is meaningful only in a multi-core

device. Because the MPC8540 is a single-core device, internally serviced interrupts are always directed

to processor 0. Permanently set and read only.

1 Interrupt directed to processor 0.

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