MPC8540 datasheet(436/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-32

Freescale Semiconductor

Programmable Interrupt Controller

Table 10-29 describes the MSR fields.

10.3.6 Interrupt Source Configuration Registers

The interrupt source configuration registers control the source of each interrupt, specifying

parameters such as the interrupting event, signal polarity, and relative priority.

10.3.6.1 External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11)

The external interrupt vector/priority registers (EIVPRs) contain polarity and sense fields for the

external interrupts caused by the assertion of any of IRQ[0:11]. The format of the EIVPRs is

shown in Figure 10-25.

Figure 10-25. External Interrupt Vector/Priority Registers (EIVPR0

–EIVPR11)

Table 10-29. MSR Field Descriptions

Bits

Name

Description

0–27

—

Reserved

Status 3. Reports status of messaging interrupt 3. Writing a 1 clears this field.

0 Messaging interrupt 3 is not active.

1 Messaging interrupt 3 is active.

Status 2. Reports status of messaging interrupt 2. Writing a 1 clears this field.

0 Messaging interrupt 2 is not active.

1 Messaging interrupt 2 is active.

Status 1. Reports status of messaging interrupt 1. Writing a 1 clears this field.

0 Messaging interrupt 1 is not active.

1 Messaging interrupt 1 is active.

Status 0. Reports status of messaging interrupt 0. Writing a 1 clears this field.

0 Messaging interrupt 0 is not active.

1 Messaging interrupt 0 is active.

10 11 12

15 16

MSK

PRIORITY

VECTOR

Reset

1000_0000_0000_0000_0000_0000_0000_0000

Offset

EIVPR0 0x5_0000, EIVPR1 0x5_0020, EIVPR2 0x5_0040, EIVPR3 0x5_0060, EIVPR4 0x5_0080,

EIVPR5 0x5_00A0, EIVPR6 0x5_00C0, EIVPR7 0x5_00E0, EIVPR8 0x5_0100, EIVPR9 0x5_0120,

EIVPR10 0x5_0140, EIVPR11 0x5_0160

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