MPC8540 datasheet(440/1302 Pages) FREESCALE

440 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-36

Freescale Semiconductor

Programmable Interrupt Controller

Table 10-33 describes the IIDRn fields.

10.3.6.5 Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3)

The messaging interrupt vector/priority registers (MIVPRn), shown in Figure 10-29, have the

same fields and format as the GTVPRn, except they apply to messaging interrupts.

Figure 10-29. Messaging Interrupt Vector/Priority Registers (MIVPRn)

Table 10-34 describes the MIVPRn fields.

Table 10-33. IIDRn Field Descriptions

Bits

Name

Description

External pin. Allows internal interrupt to be serviced externally.

0 Internal interrupt is serviced internally with int signal to the processor core.

1 Internal interrupt is directed to IRQ_OUT for external service. The behavior of the PIC is not defined

if both EP and CI are set on the same interrupt destination register.

Critical interrupt.

0 Internal interrupt is serviced internally with int signal to the processor core.

1 Internal interrupt is directed to the processor 0 as a critical interrupt with the cint signal. The behavior

of the PIC is not defined if both EP and CI are set on the same interrupt destination register.

2–30

—

Reserved

Processor 0. Indicates that processor 0 handles any interrupt. This bit is meaningful only in a multi-core

device. Because the MPC8540 is a single-core device, all interrupts that are serviced internally are

always directed to processor 0. Permanently set and read only.

1 Interrupt directed to processor 0.

11 12

15 16

MSK

A 0

000

PRIORITY

VECTOR

Reset

1000_0000_0000_0000_0000_0000_0000_0000

Offset

0x5_1600, 0x5_1620, 0x5_1640, 0x5_1660,

Table 10-34. MIVPRn Field Descriptions

Bits

Name

Description

MSK

Mask. Mask interrupts from this source.

0 An interrupt request is generated when the corresponding IPR field is set.

1 Further interrupts from this source are disabled.

Activity. Indicates an interrupt has been requested or is in-service. Note this field is read only. The

VECTOR and PRIORITY values should not be changed while MIVPRn[A] is set.

0 No current interrupt activity associated with this source.

1 The interrupt field for this source is set in the IPR or ISR.

2–11

—

Reserved

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