MPC8540 datasheet(442/1302 Pages) FREESCALE

442 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-38

Freescale Semiconductor

Programmable Interrupt Controller

10.3.7 Per-CPU Registers

The OpenPIC programming model supports multiprocessor systems of up to 32 separate

processors. As such, the OpenPIC interface specification provides for coordinating both the

requesting and servicing of interrupts among several processor cores within a single integrated

device. To fully comply with the OpenPIC specification, the PIC incorporates several of these

multiprocessor capabilities. Because the value of features such as private address space for

per-CPU registers and interprocessor interrupts is fully realized only in a multi-core environment,

their utility in this single-core device is not intuitive.

The registers in Table 10-36 are called per-CPU registers, because they would be duplicated for

each core in a multi-core device. The OpenPIC interface specifies that a copy of these registers be

available to each core at the same physical address by using the ID of the processor that initiates

the transaction to determine the set of per-CPU registers to access.

These addresses, shown in Table 10-36, appear in the memory map at the same offset for every

processor, and are called the private access space. Because the MPC8540 has only one core, there

is only one set of per-CPU registers, each register having two addresses. For example, the CTPR

is located normally at 0x6_0080 and at the private access address of 0x4_0080. While this double

mapping seems superfluous on a single-core device, the purpose of this feature is to enable user

code to execute correctly in an multiprocessor environment without needing to know which CPU

it is running on. It is included on this device to simplify the porting of such code.

An example of how the different registers are addressed in a four-core device is illustrated in

Figure 10-31. Note that when accessing a register normally, each core sources a different address.

However, when accessing the same register using the per-CPU address space, each core sources

the same address.

Table 10-36. Per-CPU Registers—Private Access Address Offsets

Offset

IPI 0 dispatch register (IPIDR0)

0x4_0040

IPI 1 dispatch register (IPIDR1)

0x4_0050

IPI 2 dispatch register (IPIDR2)

0x4_0060

IPI 3 dispatch register (IPIDR3)

0x4_0070

Current task priority register (CTPR)

0x4_0080

Who am I register (WHOAMI)

0x4_0090

Interrupt acknowledge register (IACK)

0x4_00A0

End of interrupt register (EOI)

0x4_00B0

MPC8540 Datasheet(PDF) 442 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 442 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL