MPC8540 datasheet(446/1302 Pages) FREESCALE

446 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-42

Freescale Semiconductor

Programmable Interrupt Controller

Figure 10-35. Processor Interrupt Acknowledge Register (IACK)

Table 10-40 describes the IACK fields.

10.3.7.5 Processor End of Interrupt Register (EOI)

Writing to the end of interrupt (EOI) register shown in Figure 10-36 signals the end of processing

for the highest-priority interrupt currently in-service by the processor. The write to the EOI updates

the ISR by retiring the highest priority interrupt. Data values written to this register are ignored,

and zero is assumed.

Figure 10-36. End of Interrupt Register (EOI)

Table 10-41 describes the EOI fields.

015

R 0

0000 0000 000 000

VECTOR

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x6_00A0 (see Section 10.3.7, “Per-CPU Registers.”)

Table 10-40. IACK Field Descriptions

Bits

Name

Description

0–15

—

Reserved

16–31 VECTOR Interrupt vector. Vector of the highest pending interrupt (read only)

R 0 0 0

00000000

0000000

EOI CODE

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x6_00B0 (see Section 10.3.7, “Per-CPU Registers.”)

Table 10-41. EOI Field Descriptions

Bits

Name

Description

0–27

—

Reserved

28–31 EOI CODE 0000 (write only)

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