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MPC8540 Datasheet(PDF) 449 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 449 Page - Freescale Semiconductor, Inc |
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449 / 1302 page ![]() Functional Description MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 10-45 vector associated with the interrupt source to the interrupt handler routine. The handler can further vector to different branches of interrupt handling accordingly. Note that reading IACK also negates the interrupt signal to the processor. See Section 10.3.7.4, “Processor Interrupt Acknowledge Register (IACK),” for more details. The internal in-service register (ISR) tracks all interrupts that have caused int to be asserted and that have received an IACK cycle. An interrupt is considered in-service from the time its vector is read (through an IACK cycle) until the end of interrupt (EOI) register is written, generating what the PIC considers an EOI signal. 10.4.1.1 Interrupt Source Priority Each interrupt source is assigned a priority value of 0–15 through its corresponding vector/priority register, where 15 is the highest priority. Interrupts are delivered only when the priority in the vector/priority is greater than the priority programmed into the current task priority register, CTPR. Setting a source priority to zero inhibits that interrupt. Likewise, setting the CTPR value to 15 disables all interrupts directed to the int signal. The PIC unit services simultaneous interrupts occurring with the same priority according to the following order: 1. MSG0–MSG3 2. IPI0–IPI3 3. Timer0–timer3 4. IRQ[0:11] 5. Internal0–internal31 For example, if MSG0, MSG2, and IPI0 have the same priority and generate simultaneous interrupts, they are serviced in the following order: 1. MSG0 2. MSG2 3. IPI0 10.4.1.2 Processor Current Task Priority The CTPR is set by system software to indicate the relative importance of the task running on the processor. The processor does not receive interrupts with a priority level equal to or lower than its current task priority. Therefore setting the current task priority to 15 for a particular processor prevents the delivery of any interrupt to the processor. |
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