MPC8540 datasheet(452/1302 Pages) FREESCALE

452 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

10-48

Freescale Semiconductor

Programmable Interrupt Controller

•

Polarity, sense, external pin, critical interrupt, and activity fields are reset to their default

values.

•

PIR, TFRR, TCR, MER, MSR, and MSGR0–3 are cleared.

•

MSG and timer destination fields are set.

•

The IPI dispatch registers are cleared.

•

All timer base count values are reset to zero and count inhibited.

•

The CTPR[TASKP] is reset to 0xF, thus disabling interrupt delivery to the processor.

•

The spurious interrupt vector resets to 0xFFFF.

•

The PMMRs are reset to 0xFFFF.

•

The PIC defaults to the pass-through mode (GCR[M] = 0).

•

All other registers remain at their pre-reset programmed values.

The GCR[RST] bit is automatically cleared when the reset sequence is complete.

10.5 Initialization/Application Information

This section contains initialization and application information for the PIC.

10.5.1 Programming Guidelines

The following subsections contain information about programming PIC registers.

10.5.1.1 PIC Registers

Most PIC control and status registers are readable and return the last value written. The exceptions

to this rule are as follows:

•

IPI dispatch registers and the EOI register, which return zeros on reads.

•

Activity bit (A) of the vector/priority registers, which returns the value according to the

status of the current interrupt source.

•

IACK register, which returns the vector of highest priority which is currently pending, or

the spurious vector.

•

Reserved fields always return 0.

The following guidelines are recommended when the PIC unit is programmed in mixed mode

(GCR[M] = 1):

•

All PIC registers must be located in a cache-inhibited and guarded area (through the

processor MMU).

•

The PIC portion of the address map must be set-up appropriately.

MPC8540 Datasheet(PDF) 452 Page - Freescale Semiconductor, Inc

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